Multiplier circuits which receive input data in serial format are typically much more size efficient to implement in hardware than are multiplier circuits which operate with input data in parallel format. Reasons for the truth of this statement include the fact that signals in a serial data multiplier may be routed more simply and efficiently than when the data is in a parallel format. Also, mathematical functions may be more efficiently implemented from a hardware standpoint when input data is in the serial form. High data throughtput may be achieved in a serial data multiplier by using a pipeline architecture and by minimizing worst case delay paths in the pipeline. In contrast, many known Booth's or Modified Booth's algorithm multiplier architectures are slower because the nature of the algorithm requires the accumulation of a product wide result which has the disadvantage of long carry chains. Therefore, a serial data multiplier is typically faster than many known multiplier architectures. However, the known serial data multipliers are not typically capable of multiplying signed input operands. When signed input operands are multiplied, others have typically used a parallel input data architecture.